发明名称 REDUNDANT BLOCK SWITCHING CIRCUIT
摘要 PURPOSE:To improve the yield of a chip and to reduce a chip unit price by providing a redundancy switching circuit with high relief efficiency by suppressing the increment of a chip area and the increment of power consumption and delay time by a redundant block to the minimum. CONSTITUTION:This circuit is a redundant block switching circuit 2 with the structure in which one of 3 to (N+1) of first functional blocks (N+1) is selected and it can be connected to second functional blocks in one to one in an LSI with the structure in which M first functional blocks, N(1<N<M) first functional blocks as redundant functional blocks, M second functional blocks corresponding to the first functional blocks one to one, and the redundancy switching circuit to select the connection of the first functional blocks and the second functional blocks are included in one chip.
申请公布号 JPH0793172(A) 申请公布日期 1995.04.07
申请号 JP19930237084 申请日期 1993.09.24
申请人 NEC CORP 发明人 KIMURA TORU
分类号 G06F12/16;G06F11/20;G06F15/16;G06F15/80;G11C29/00;G11C29/04;H03K17/00;H03K17/693;(IPC1-7):G06F11/20 主分类号 G06F12/16
代理机构 代理人
主权项
地址