| 摘要 |
PURPOSE: To accelerate the data processing speed of a signal processor. CONSTITUTION: One or more arithmetic and logic units 14 and a signal processing unit provided with one multiplier 12 can be changed corresponding to the setting of masking units 44 and 54 capable of setting the contents of an input data word beforehand before being processed by the signal processing unit so as to accelerate the data processing speed of the signal processor 10 supplied with the input data of an (n)-bit, word length. The masking units 44 and 54 are made independently settable for the respective bits of the input data word, the masking units 44 and 54 are set beforehand by the contents of two registers provided with the same word length as the input data word and the operations of the masking units 44 and 54 are decided by the bit contents of the register corresponding to the input data word. |
