发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To enable the appropriate processing and output of information without enlarging the capacity of a memory. CONSTITUTION:A bus 2 is connected mutually among a CPU 1, the memory 3 storing the information and an I/O a device 6 for performing the input/output of the information. A DMAC 5 is also connected to the bus 2 and the DMAC 5 releases the bus 2 from the CPU 1 corresponding to the request of the I/O device 6. An arithmetic unit 4 is connected to the bus 2 as well and the arithmetic unit 4 reads and processes the information inside the memory 3 by each prescribed amount at the time of the release of the bus 2. When the processing by the arithmetic unit 4 is completed, the information inside the arithmetic unit 4 is successively supplied to the I/O device 6 and outputted.
申请公布号 JPH0793512(A) 申请公布日期 1995.04.07
申请号 JP19930236688 申请日期 1993.09.22
申请人 TOSHIBA CORP 发明人 OKAZAKI YOSHIHIKO
分类号 G06F13/28;G06F5/00;G06T1/00;G06T9/00;H04N5/78;(IPC1-7):G06T1/00 主分类号 G06F13/28
代理机构 代理人
主权项
地址