| 摘要 |
PURPOSE:To output a redundant-address coincidence signal stably and at high speed and to reduce an area occupied by a chip by a method wherein a redundant-address detection circuit and an redundant-address decoder which is provided with a redundant-address coincidence and noncoincidence signal generation function are installed. CONSTITUTION:Fuse decoders inside redundant-address decoders which are connected in common to a signal for an inverter generate a coincidence signal by judging that FUSEs 0-0, 0-1 are contents of a programmed address and of an address bus, or they judge that both are not coincident. An address- coincidence-signal generation circuit is composed of transistors 219 to 223 and of an inverter 226, and an address-noncoincidence-signal generation circuit is composed of a NAND logic gate 225. When an address coincidence signal RREN0 judges that both fuse decoders 0-0, 0-1 noncoincident by responding to an address signal input, its logic state is shifted from a high level to a low level. When any one of the fuse decoders generates a coincidence signal, the logic state is not changed. |
