发明名称 GATE CONTROL METHOD
摘要 PURPOSE:To prevent the illegal access of a memory by performing main gate open on the condition of all gates open. CONSTITUTION:Plural gates 2-4 and flip-flop(F/F) circuits 6-8 are provided at the preceding step of a main gate connected to a ROM. In this case, by inputting respective condition data such as address signals or data signals to the respective gates 2-4 in a prescribed order, the respective gates 2-4 are opened, and the respective F/F circuits 6-8 are set. When any condition data not matched with previously decided condition data are inputted, a gate 5 and an F/F circuit 9 close the F/F circuits 6-8. Then, on the condition that all the plural gates 2-5 are opened, the main gate is opened, and signals are outputted from the F/F circuit 8.
申请公布号 JPH0793222(A) 申请公布日期 1995.04.07
申请号 JP19940004130 申请日期 1994.01.19
申请人 CASIO COMPUT CO LTD 发明人 SAKURAI KEIICHI;KUMAGAI SHO
分类号 G06F12/14;G06F21/24;(IPC1-7):G06F12/14 主分类号 G06F12/14
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