| 摘要 |
PURPOSE:To enhance the operating speed of a basic cell by reducing the parasitic resistance in diffusion region and to realize high density of transistor by decreasing the areas of wiring region and power supply wiring. CONSTITUTION:Fig. (a) shows a layout including a second metal layer and Fig. (b) shows the layout of underlying layer by removing the second metal layer. p-diffusion region 4 and n-diffusion region 3 are arranged vertically and power supply wirings are provided at the upper and lower ends thereof. In order to reduce parasitic resistance, the diffusion regions are covered substantially entirely with a first metal layer. Second and third metal layers are used for interconnection of basic cells. The wiring area is reduced by superposing first and second metal layers for the power supply wiring, wiring the second metal layer in the wiring region 20 between a power supply wiring and a ground wiring 9, and arranging additional basic cells contiguously in vertical direction while sharing the power supply wiring and the ground wiring. |
