| 摘要 |
PURPOSE:To obtain the title memory device in which a stable operation is ensured under a low operating voltage even when a cell ratio is made small, whose power consumption is low and which is highly integrated regarding an SRAM. CONSTITUTION:A capacitor 19 is connected across a word line WL and a gate for an nMOS transistor 17, and a capacitor 20 is connected across the word line WL and a gate for an nMOS transistor 18. A resistance 21 is connected across the gate for the nMOS transistor 17 and a node 23, and a resistance 22 is connected across the gate for the nMOS transistor 18 and a node 24. Thereby, a memory cell is constituted. |
