发明名称 MULTIPROCESSOR
摘要 <p>Data are transferred between arithmetic units 11 to 1N and local memories 21 to 2N for through data buses 61 to 6N parallel processing. The data bus 61 connected to one arithmetic unit 11 can be connected to other data buses 62 to 6N through a mutual connection network (5), and thus by operating only one arithmetic unit 11 data can be transferred through the data buses 61 to 6N and the mutual connection network (5) to and from all the local memories 21 to 2N. In this way, a plurality of arithmetic units are allowed to correspond to a plurality of local memories to execute parallel processing, and any one of the arithmetic units can easily make access to any of the local memories.</p>
申请公布号 WO1995009399(P1) 申请公布日期 1995.04.06
申请号 JP1994001479 申请日期 1994.09.07
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