| 摘要 |
A plurality of electrically conductive leads (45) are formed on an electrically insulative substrate (35) by tape automated bonding methods. The leads (35) extend from peripherally disposed test terminals (60) to centrally disposed interconnect pads (55) and are aligned therebetween with bond pads (30) that are disposed near a perimeter (32) of a face (17) of a chip (15). The leads (35) are connected to the bond pads (30) and are encapsulated with a cement, and the substrate is adhered to the chip face. The leads (35) are then severed closely peripheral to the bond pads (30), disconnecting the test terminals (60) from the chip (15). The chips that pass the testing are connected via the interconnect pads (55), which may be arranged in a pad grid array, to matching terminals (90) in a package (95). |
