Error correction for digital video data.

摘要

In an apparatus for processing input N-bit digital video data with an error correction parity, the input N-bit digital video data includes each one sample of higher-order-N-bit data and a plurality of samples of lower-order-(M - N)-bit data, wherein M > N. An error correction circuit corrects an error of input N-bit digital video data, outputs error-corrected N-bit digital video data, and generates an error detection signal representing an error which can not be corrected. Further, a data combining circuit converts the error-corrected N-bit digital video data into M-bit digital video data, and an error classifying circuit classifies the error detection signal into a first error detection signal representing an error of the each one sample of the higher-order-N-bit data and a second error detection signal representing an error of the plurality of samples of the lower-order-(M - N)-bit data. An error concealment circuit performs an error concealment process for the converted M-bit digital video data based on only the first error detection signal. <IMAGE>