| 摘要 |
A metallization and bonding process for manufacturing a power semiconductor device comprises a step of deposition of a first metal layer (12;25) over the entire surface of a chip; a step of selective etching of the first metal layer (12;25) to form desired patterns of metal interconnection lines between components previously defined; a step of deposition of a layer (13) of passivating material over the entire surface of the chip; a step of selective etching of the layer (13) of passivating material down to the first metal layer (12;25) to define bonding areas (14,15;27,28) represented by uncovered portions of the first metal layer (12;25); a step of deposition of a thick second metal layer (16;29) over the entire surface of the chip; a step of selective etching of the second metal layer (16;29) down to the layer (13) of passivating material to remove the second metal layer (16;29) outside said bonding areas (14,15;27,28); and a step of connection of bonding wires (17,18;30,31) to the surface of the second metal layer (16;29) in correspondance of said bonding areas (14,15;27,28). <IMAGE> |
