发明名称 Method and apparatus for power-source wiring design of semiconductor integrated circuits
摘要 Disclosed is an apparatus for power-source wiring design of semiconductor integrated circuits including a theoretical lattice setting device for setting lattice to divide the surface of a semiconductor substrate sectional regions, an extracting device for extracting electric characteristics of each sectional region, and an operation device for obtaining circuit characteristics of each sectional region. Also disclosed is an apparatus for power-source wiring design of semiconductor integrated circuits comprising a trial circuit generating device for generating a circuit model of power-source.ground wiring of a semiconductor integrated circuit on trial, an analysis device for analyzing electric characteristics of each sectional region of the circuit model, and a comparison device for comparing the analysis result of electric characteristics obtained by the analysis device to the circuit model with an analysis result of electric characteristics previously obtained by the analysis device to a circuit model previously obtained, and estimating the former analysis result, and an improving plan generating device for generating information of a plan to improve the circuit model preferably in accordance with the comparison estimation result by the comparison device, and giving the information to the trial circuit generating device.
申请公布号 US5404310(A) 申请公布日期 1995.04.04
申请号 US19900599030 申请日期 1990.10.17
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MITSUHASHI, TAKASHI
分类号 H01L21/822;G06F17/50;H01L21/82;H01L27/04;(IPC1-7):G06F15/60 主分类号 H01L21/822
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