发明名称 |
Parallel processor which processes instructions, after a branch instruction, in parallel prior to executing the branch instruction and its parallel processing method |
摘要 |
In a typical operating system, one-third of a program consists of branch instructions. This means a performance of a processor of a typical operating system depends greatly on whether or not an instruction before and after a branch instruction can be executed in parallel. In order to provide a high performance processor with parallel processing, provided is a structure with a plurality of operating units and a plurality of registers where a set of registers are specified with the same address. A selection sequence of registers is stored by a plurality of selection sequence storages. Contents of registers are determined or not depending on the information stored in a plurality of determination identification storages. A register is specified by a register selector according to the contents of the selection sequence storages. This register selector is also used to update the contents of the selection sequence storages. The contents of the determination identification storages are rewritten by a determination identifier when the contents of a register proves to be a correct result.
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申请公布号 |
US5404551(A) |
申请公布日期 |
1995.04.04 |
申请号 |
US19910795145 |
申请日期 |
1991.11.20 |
申请人 |
FUJITSU LIMITED |
发明人 |
KATSUNO, AKIRA |
分类号 |
G06F7/00;G06F9/38;(IPC1-7):G06F9/28;G06F9/30 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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