| 摘要 |
In a digital filter, a plurality of delay elements D1 Dn are serially connected to one another, and taps for obtaining delay signals being different in delay time from one another are provided at respective connecting portions. Outputs from a plurality of multipliers M0 - M3 are added together by an adder A, and the result is outputted to an output terminal of the digital filter. Signal selecting means S00 - S3n are switched on or off between the plurality of taps and the input terminals of the plurality of multipliers. The multipliers M0 - M3 can be connected to optional taps, and, by use of a relatively small number of multipliers, a plurality of delay signals being different in delay time from one another are formed into a composite output signal while the delay times and the signal levels being widely selected.
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