| 摘要 |
<p>PURPOSE:To reduce the power consumption of the whole system by making an address bus inactive when a stop instruction or wait instruction is executed. CONSTITUTION:This device is provided with an address bus control means 2 for fixing the potential of terminals, outputting addresses of external address buses 5a and 5b, forcibly at a set level; after each instruction is executed, an address latch enable signal control means 9 outputs an address latch enable signal for extracting only an address from a multiplex signal consisting of the address and data only once to an address latch means 4 outside a single-chip microcomputer 1 and the address latch means 4 is made to latch the set level of the address.</p> |
