| 摘要 |
<p>PURPOSE:To reduce noises to a power supply line and transient power consumption due to the simultaneous variation of external output terminals of an address bus, etc., and to prevent a system from malfunctioning owing to a voltage drop by outputting data consisting of plural bits on a time-division basis at specific intervals of bit width in synchronism with synchronizing clock timing when the number of variation bits is larger than a predetermined value. CONSTITUTION:A comparator 6 compares last data stored in a temporary register 5 with current data. A variation quantity decision means 7 when deciding that data vary by >=16 bits sends a control signal 11 indicating one-wait insertion to a bus cycle control unit 3 and also sends a high-level output control signal 12 to tri-state buffer groups 8 and 9 at timing of pH2. The high active tri-state buffer group 9 becomes active to output the low-order 16 bits to an external output terminal 10 first and then the remaining low-order 16 bits at next pHI respectively.</p> |
