| 摘要 |
PURPOSE:To improve the dimensional uniformity of gate length of an MOS transistor, by defining the gate length of the gate electrode of an MOS transistor of a trench capacitor cell by using a punched-out pattern. CONSTITUTION:Poly silicon doped with N-type impurities is deposited on a substrate, a resist pattern 23 for forming a gate electrode 22 is formed on the poly silicon, it is etched by using a resist pattern 23 as a mask, and the gate electrode 22 of an MOS transistor is formed. In this case, the upper part of the gate electrode 22 is etched so as to cover a part on a silicon oxide film. The gate length (the length in the direction of a channel which faces the substrate surface via a gate insulating film 19) of the gate electrode 22 is defined by a punched-out pattern of a wiring layer containing a poly silicon wiring 16, so that the dimensional uniformity of the gate length of the MOS transistor can be improved. |
