发明名称 Datenübertragungsnetzwerk für Multiprozessorsysteme.
摘要 A data switching device embodying the invention mainly includes two input circuits, two output circuits, and a load regulating circuit. The two input circuits are respectively connected to two source devices transmitting data messages. The two output circuits are respectively connected to two destination devices toward which the messages are switched. The load regulating circuit derives switching instructions as a function of external load information supplied by the destination means and provides other load information intended for the source devices. Switching control means based on a priority management are divided out over the input and output circuits. The switching device is usable to set up divided load-regulated and controlled switching networks intended notably for symbol processing multiprocessor systems.
申请公布号 DE68917679(T2) 申请公布日期 1995.03.30
申请号 DE1989617679 申请日期 1989.10.13
申请人 OFFICE NATIONAL D'ETUDES ET DE RECHERCHES AEROSPATIALES, O.N.E.R.A., CHATILLON-SOUS-BAGNEUX, HAUTS-DE-SEINE, FR 发明人 CUBERO-CASTAN, MICHEL, F-31400 TOULOUSE, FR;DURRIEU, GUY, F-31650 SAINT ORENS, FR;LECUSSAN, BERNARD, F-31130 BALMA, FR;LEMAITRE, MICHEL, F-31500 TOULOUSE, FR
分类号 G06F15/173;H04L12/56;(IPC1-7):G06F15/16;H04L12/54 主分类号 G06F15/173
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