| 摘要 |
<p>A built-in self-test circuitry includes a design under test (32) and a self-test processor (31). Included within the design under test (32) is a plurality of scan row registers. The self-test processor includes a command processing means and a signal generating means. The command processing means receives information which indicates the configuration of the scan row registers. The signal generating means generates control signals which control the built-in self-testing of the circuit. The control signals are based on the information received by the command processing means. In the preferred embodiment, the command processing means includes a shift means (43), a load means (44), and a signature means (45). The shift means (43) receives information which indicates a number of bits in each scan row register. The load means (44) receives information which indicates a number of loads into the scan row registers. The signature means (45) receives information which indicates a bit length of signature registers (250, 251, 259) used to generate a checksum. The signature means (45) additionally receives information which indicates a number of scan row registers.</p> |
