| 摘要 |
<p>The device (3) comprises, in the form of a phase-lock loop, a phase comparator (30), a filter (31), an oscillator (32) producing a local clock signal (S1) and two frequency divide-by M circuits (33, 34). These dividers receive the local signal (Sl) the frequency (fl) of which is slaved to N times the frequency (fp) of a pilot clock signal (Sp), with M<N, and are looped back onto the inputs of the comparator (30). The second divider (34) is reinitialised to the frequency (fp) of the pilot signal (Sp). A loading circuit (35) loads high-order stages of a counter included in the first divider (33) with a word (WORD) added to binary elements stored in the high-order stages of a counter included in the second divider (34), following a reinitialisation of the second divider (34) following general initialisation of the device (3). <IMAGE></p> |
