发明名称
摘要 <p>PURPOSE:To establish resynchronization in a short period by outputting a logical signal contrary to an input condition to a second transmitting-reception means with a first transmitting-reception means, and repeating, for plural times, to output the received logical signal to the first transmitting/receiving means with the second transmitting-reception means. CONSTITUTION:A data bit is outputted between a first transmitting means and a second transmitting means at every set time t0. When pull out is detected, the first transmitting-reception means outputs a first signal of a logic contrary to the input condition to the second transmitting-reception means. The second transmitting-reception means to have received the first signal confirms that the input condition has changed, and outputs a second signal of the same logic as the first signal to the first transmitting-reception means. Further, the above action is repeated for plural times, and the synchronization is obtained. In such a case, the exchange time of the signal is set shorter than the time t0.</p>
申请公布号 JPH0728315(B2) 申请公布日期 1995.03.29
申请号 JP19870271784 申请日期 1987.10.29
申请人 发明人
分类号 H04L5/14;H04L7/04;H04L25/38;(IPC1-7):H04L25/38 主分类号 H04L5/14
代理机构 代理人
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