| 摘要 |
<p>The device comprises two data inputs (E1, E2) and two data outputs (S1, S2), and a matrix of memory cells (CMij) each able to store one data item, the number of cells depending on the size of the data set to be stored sequentially, as well as a data write bus (BEij) and a data read bus (PLij) for each row (Li) of cells of the matrix, to which buses all the cells of the said row are linked. Controllable switching means (TE1...TE3,2) possess a first state in which they connect one of the data inputs (E1) to the write bus (BE1) of a first end row (L1) of the matrix and one of the data outputs (S1) to the data read bus (BL3) of the opposite end row (L3), and a second state in which they connect the other data input (E2) to the write bus (BE3) of the opposite end row (L3) and the other data output (S2) to the read bus (BL1) of the said first end row (L1). In their two states they connect the read bus of each row to the write bus of the neighbouring row. Finally, means (MG, BCLj, BCEj) sequentially and cyclically command, in pairs of columns of the matrix, the writing and reading, respectively, of data to and from all the cells of the two columns of the relevant pair in order in respect of the successive ranks of the said columns, this order being predetermined and different in each of the two states. <IMAGE></p> |
