发明名称 MUTE CIRCUIT
摘要 PURPOSE:To obtain a mute circuit which features the low-noise signal route and high input sensitivity and is suited to the semiconductor integration by providing the current mirror circuit to the input with the differential amplifier used for control. CONSTITUTION:When mute signal 14 is at low level, the transistor of the mute signal input circuit becomes nonconductive and output 12 shows the high voltage. Thus, differential paired transistor Q54 and Q55 constituting the mute circuit conduct. As a result, the emitter current of signal amplifying transistor Q47 flows to transistor Q54 of the mute circuit, and thus the amplified signal is delivered from Q54. In case the signal 14 is at high level, the transistor of the mute signal input circuit becomes nonconductive. And transistor Q53 and Q56 conduct contrarily to the above at the differential pair circuit, but no current flows to the output transistor side thus to obtain the output of zero.
申请公布号 JPS54128251(A) 申请公布日期 1979.10.04
申请号 JP19780035534 申请日期 1978.03.29
申请人 HITACHI LTD 发明人 WATANABE KAZUO;IENAKA MASANORI;KOMINAMI YASUO;HONMA KIYOSHI
分类号 H03F1/00;H03D3/00;H03G3/10;H03G3/34 主分类号 H03F1/00
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