Circuit arrangement of an interface for switching system controllers interconnected via a parallel bus system

摘要

The circuit arrangement of an interface for a parallel bus system which is designed as an integrated circuit is intended to be extended by means of an external connection of a simple memory with no special configuration in such a way that an increased information flow for specific applications is enabled. An additional memory controller, to which a random-access memory located outside the circuit arrangement is connected, is located within the bus interface. This memory can store a plurality of complete packets for both the transmit and receive directions and is connected via a bus manager upstream of the transmit buffer and downstream of the receive buffer. This memory is operated by the memory controller as a FIFO memory, a dedicated memory area whose capacity corresponds to the maximum possible packet size being provided for each packet to be stored. Only one additional memory controller needs to be provided within an interface designed as an integrated circuit for the operation of an additional memory. The memory controller is designed in such a way that a simple random access memory (RAM), which is operated as a FIFO memory, can be used.