发明名称 |
Dram control Circuit. |
摘要 |
<p>A DRAM control circuit according to the present invention, comprising a DRAM, a DRAM controller adapted for receiving an address, write data, and a data rewrite command from a host controller and designating a row address and a column address to the DRAM, and a column address strobe signal control circuit, causes pseudo column address strobe signal DCASq-N to have "L" level to read the contents of the address when column address strobe signal DCAS-N and read signal RD-N have "L" level, causes pseudo column address strobe signal DCASq-N to have "H" level to set an input/output terminal I/O to high impedance when the read signal RD-N has "H" level, further causes pseudo write signal WR-q to have "L" level to output write data to a data bus when the input/output terminal I/O remains at the high impedance, and rewrites the contents of the address to the write data when the pseudo column address strobe signal DCASq-N is caused to have "L" level. <IMAGE></p> |
申请公布号 |
EP0644550(A2) |
申请公布日期 |
1995.03.22 |
申请号 |
EP19940114394 |
申请日期 |
1994.09.13 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
ISHIKAWA, OSAMU, C/O OKI ELECTRIC IND.CO.,LTD.;ITO, TOSHIKAZU, C/O OKI ELECTRIC IND.CO.,LTD. |
分类号 |
G11C7/22;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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