PLL Frequency synthesizer circuit.

摘要

A PLL frequency synthesizer is disclosed, which comprises a voltage controlled oscillator (20), and a comparison frequency divider (13) for dividing a frequency of the output signal from the voltage controlled oscillator (20) to output a comparison signal. A phase comparator (17) in the synthesizer compares a phase of a reference signal to be fed thereto with a phase of the comparison signal, and generates a first and second phase difference signals, based on its comparision result. The synthesizer further includes a charge-pump circuit (21) operated based on the first and second phase difference signals, and having an output terminal (OT1) connected to the voltage controlled oscillator (20). The charge-pump circuit includes a first bipolar transistor (T1) connected between a high-potential power supply (Vcc) and the output terminal (OT1), and a second bipolar transistor (T2) connected between a low-potential power supply (GND) and the output terminal (OT1). The first and second bipolar transistors are controlled based on the first and second phase difference signals, respectively. At least one of the first and second bipolar transistors is an emitter-follower type. <IMAGE>