CMOS circuit providing 90 degree phase delay

摘要

A high speed clock recovery system that provides a precise 90 DEG phase shift at the incoming NRZ data rate by using a series of differential inverters and controlling their delays in accordance with the corresponding delays of differential inverters of a ring oscillator that is part of a phase-locked loop. More particularly, the incoming NRZ data and the phase shifted data are fed to an exclusive OR that provides an output signal including a frequency component of the originating clock of the NRZ data. The phase-locked loop further includes a phase detector which is responsive to the output of the exclusive OR and the ring oscillator. Thus, once the loop locks, the ring oscillator is synchronized to the frequency of the originating clock for the NRZ data. By slaving the differential inverters of the phase shifter and the ring oscillator to the same delays, the phase shifter provides a dynamically adjusted delay of precisely 90 DEG at the originating clock frequency of the incoming NRZ data.