发明名称 |
Simulator for conducting timing analysis of a circuit |
摘要 |
There is disclosed a simulator having timing error detecting from input and output signal level changes. Different timing error verifications are carried out for respective elements. In similar constructions, different test rule error verifications are also carried out for the respective elements as a function of the contents of a test rule check value definition file. |
申请公布号 |
US5400270(A) |
申请公布日期 |
1995.03.21 |
申请号 |
US19920933711 |
申请日期 |
1992.08.24 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
FUKUI, YOSHIAKI;YOSHIDA, NORIO;KISHIMOTO, YASUNORI;INOUE, YOSHIO |
分类号 |
G06F11/25;G01R31/30;G01R31/3183;G06F17/50;(IPC1-7):G06F15/60 |
主分类号 |
G06F11/25 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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