| 摘要 |
A dynamic RAM comprises first and second memory cell arrays respectively outputting holding data to corresponding bit lines when selected, sense amplifier means having amplifying MOS transistor for amplifying output of the bit lines of the first and second memory cell arrays, first and second transfer gate means respectively providing corresponding to the first and second memory cell arrays and controlling establishing and blocking connection between corresponding memory cell array and the sense amplifier means, first and second driver means respective provided corresponding to the first and second transfer gate means and generating gate control voltages for corresponding transfer gate means. Each of the first and second driver means comprises intermediate voltage setting means operable at a first voltage and a second voltage different from the first voltage, having the same conductive type with the amplifying MOS transistor, and at a stand-by state, for setting the gate control voltage of the transfer gate means at a third voltage which is level shifted from the first voltage in an extent corresponding to a threshold voltage of the MOS transistor, and selection voltage setting means for setting the gate control voltage of the transfer gate means corresponding to the memory cell array of the selected side at the first voltage and setting the gate control voltage of the transfer gate means corresponding to the memory cell array of the non-selected side at the second voltage, upon selection of the memory cell arrays.
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