Hold-type latch circuit with increased margin in the feedback timing and a memory device using same for holding parity check error

摘要

A hold-type latch circuit which features an increased operation margin. A feedback circuit feeds the data output logic state of a non-inversion data output terminal of the latch circuit back to a data input terminal thereof, to increase a margin in the setup time _t and holding time _t in controlling the data holding capability of the latch circuit, thereby to increase the margin of thereof.