| 摘要 |
PURPOSE: To block a memory operation correcting a state at the time of a shift mode and to shift all states capable of scanning by controlling a clock input and control signal to a memory array. CONSTITUTION: The memory array 10 is composed of a storage element 20, a control and address resistor 30, data input and output lines 40, 50 and a timing generating circuit 280. An external clock is received with the timing generating circuit 30 and a self timed internal clock pulse is transmitted. The resistor 30 is scanned with an array control and address resistor through a pin 55, and a bit is sent out from a pin 95 with resistors 60, 65, 70-90 shifted. A memory array resistor is provided with independent inputs 61, 66, 71-91, and the address and control information is loaded in a non-shift mode. A scanning output 95 is made to be a next scanning input in the memory array having plural chips. Also, when a pulse is generated from the timing generating circuit 280, all pulses are invalidated at the time of the shift mode, and independent pulses are added. |
