LAYOUT PATTERN VERIFICATION SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT,申请号JP19930220196-传众专利搜索

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发明名称	LAYOUT PATTERN VERIFICATION SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要
申请公布号	JPH0774262(A)	申请公布日期	1995.03.17
申请号	JP19930220196	申请日期	1993.09.03
申请人	SHARP CORP	发明人	TAKAO MASATO
分类号	H01L21/82;G06F17/50;(IPC1-7):H01L21/82	主分类号	H01L21/82
代理机构		代理人
主权项
地址

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