VERSATILE ARITHMETIC UNIT FOR HIGH SPEED SEQUENTIAL DECODER

摘要

An arithmetic unit for a decoder for data encoded by convolution encoding. The arithmetic unit includes two channels, a main metric channel and a delta metric channel. In the main metric channel a metric is computed for a received symbol branch with respect to check bits from an encoder replica which is fed with a data bit, assumed to be a zero. The delta metric channel computes a delta metric for the same branch. At the end of the computations the sign of the computed delta metric is used to control the changing of the data bit to a one and the adding of the computed delta metric to the metric in the main metric channel.