| 摘要 |
PURPOSE: To realize a frequency conversion at a high speed with a circuit, which consumes less power as compared with conventional technologies such as the phase locked loop. CONSTITUTION: An odd number of inverters 201-203 accept a positive power supply voltage VDDR and a negative power supply voltage VSSR through a binary current tree. The voltage-controlled current tree has PMOS and NMOS networks and is constituted in three banks 204, 210, 216, 207, 213, and 219. The PMOS and NMOS networks control the current of a ring and delays through each inverter. When all transistors in the binary current tree and turned on, the oscillation frequency of a ring oscillator becomes the maximum and, when a certain transistor pair is turned off, the power supply current of the ring decreases and the oscillation frequency becomes lower. The ring saves the power consumption of a programmable frequency generator by turning on/off a NAND gate 202. |
