| 摘要 |
PURPOSE:To improve the operation speed of a memory control circuit in a space digital computer incorporating a software error accumulation preventing means. CONSTITUTION:Data which is read out of a memory 12 is error-corrected in an ECC circuit 13 and it is inputted to a main arithmetic part through a data register 15 and a three state buffer 18. The ECC circuit outputs an error correction signal to a timing circuit 14 when an error is corrected. The timing circuit outputs a wait signal to the main arithmetic part and temporarily stops an operation. Then, it outputs a write signal, to the memory, and a selection signal to a data selection circuit 19 after a prescribed time is elapsed. The write data selection circuit 19 outputs data from the data register to the ECC circuit as the write signal, and the ECC circuit generates a check bit and outputs data and the check bit. Data and the check bit from the ECC circuit are rewritten into an address position held by the address register of the memory. |
