| 摘要 |
PURPOSE:To speed the multiplication of data by adjusting the timing of clock by using the only output between the master part and the slave part of a T flip-flop operating with the half frequency of data late. CONSTITUTION:The 1st-3rd selector circuits 1-3 and a timing circuit consisting of a T flip-flop master part 4 and a T flip-flop slave part 5. A clock 1/2CK is provided with the frequency which is a half of that of the data late of a signal outputted from the 3rd selector circuit at the final stage. The clock 1/4CKs 1 and 2 have the frequency which is a fourth of the data late. The clock 1/2CK is given from a synchronizing circuit to the reverse input terminal of the clock of the master part 4 and to the clock input terminal of the slave part 5. In short, the timing of clock is adjusted by using the output of the master part 4 of the T flip-flop operating with the frequency which is a half of that of data late and the output of the slave part 5. |
