Clock-synchronous semiconductor memory device

摘要

A signal-input buffer (116; 206, 210; 108) reaches a passage state if an external clock signal Ka is in an inactive state, and generates an internal signal in response to an external signal, and it reaches a blocking state if the external clock signal is in an inactive state. A data transfer from a master data register (MDTBR), which stores the data in a DRAM arrangement (102) by means of a slave data register (SDTBR), is executed in response to a determination of a use of the slave data register. The slave data register stores the data to be transferred into an SRAM arrangement (104) or those data which are to be accessed externally. This provides a synchronous semiconductor memory device which can be accessed at high speed and without waiting. Furthermore, the internal clock signal is activated for a predetermined time in response to an activation of an external clock signal in order to ensure accurate internal operation timing. <IMAGE>