| 摘要 |
A gate array device (10) includes a plurality of static random access memory cells (11). Each memory cell (11) comprises n-channel pass gate transistors (12, 14), n-channel drive transistors (16, 18), and p-channel transistors (20, 22). All transistors within the memory cell (11) are approximately of the same size. A resistance element (23) connects to the p-channel transistors (20, 22) in each memory cell (11), generating a new apply voltage ( Vcr). The resistance element (23) effectively reduces the size of the p-channel transistors (20, 22) to below the size of the drive transistors (16, 18). By effectively reducing the size of the p-channel transistors (20, 22), the speed, accuracy, and stability of the memory cell (11) are enhanced despite the similar sizes of the transistors in the gate array device (10). <IMAGE> |
