发明名称 Central processing unit including two-valued/n-valued conversion unit
摘要 A central processing unit comprises a bidirectional circuit for converting a binary data and a binary address supplied from a binary logic circuit in the CPU into n-valued (n is an integer of 3 or larger) data and an n-valued address, respectively, and transmitting converted signals to the outside, and for converting n-valued data and an n-valued address supplied from the outside into binary data and a binary address, respectively, and transmitting converted signals to the binary logic circuit.
申请公布号 US5398327(A) 申请公布日期 1995.03.14
申请号 US19920841627 申请日期 1992.02.26
申请人 SHARP KABUSHIKI KAISHA 发明人 YOSHIDA, YUKIHIRO
分类号 G06F13/16;G06F13/36;G06F13/40;G06F13/42;H03M7/06;(IPC1-7):G06F13/00 主分类号 G06F13/16
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