发明名称 |
Access time speed-up circuit for a semiconductor memory device |
摘要 |
A semiconductor memory device includes two latch circuits, each for holding data corresponding to a single normal address. When sequentially used, one after the other, one latch circuit can be storing new data while the other latch circuit outputs its data to the page decoder for subsequent output. Thus, data access delay times for page mode operation are further reduced because the delay which typically results from addressing a normal address is eliminated.
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申请公布号 |
US5398213(A) |
申请公布日期 |
1995.03.14 |
申请号 |
US19930133471 |
申请日期 |
1993.10.08 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
YEON, EUNG-MOON;LIM, YOUNG-HO |
分类号 |
G11C11/401;G11C7/10;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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