发明名称 Memory programming load-line circuit with dual slope I-V curve
摘要 A non-volatile memory device is described. The memory device includes a memory array and current regulating circuitry coupled to the memory array. The memory array includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line such that the first memory cell receives a first current during programming of the first memory cell and the second memory cell receives a second current during programming of the second memory cell. The current regulating circuitry regulates the first and second currents during programming of the first and second memory cells such that when the first cell is being programmed and the second cell is not being programmed, the circuitry limits the first current flowing through the first bit line for programming the first memory cell to be substantially equivalent to the first current if the first and second memory cells are being programmed substantially at the same time. The current regulating circuitry allows the current-voltage characteristic of the programming load line to be controlled such that the characteristic, represented as a curve, may have two slopes and the shape and slopes of the curve may be adjusted independently.
申请公布号 US5398203(A) 申请公布日期 1995.03.14
申请号 US19930115217 申请日期 1993.09.01
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 PRICKETT, JR., BRUCE
分类号 G11C16/30;(IPC1-7):G11C11/34 主分类号 G11C16/30
代理机构 代理人
主权项
地址