| 摘要 |
The method includes the steps of sequentially forming an insulating film (2), a gate (3), a gate insulating layer (4), and an Si layer (5) for channel source and drain regions on the Si substrate (1), implanting Si ions into the lyaer (5), secondly implanting Si ions thereinto by using a source and drain ion implantation mask (6) formed on the channel region to remove the mask (6), forming a channel and a source and drain (7) region by annealing, thereby differently performing the Si ion implantations to reduce the EHP generation at the grain boundary formed at the junction part.
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