发明名称 ACCESS SYSTEM FOR EEPROM
摘要 <p>PURPOSE:To lessen the number of times of writing by checking rewriting of the same data on the occasion of writing in EEPROM. CONSTITUTION:In response to a write request from another host, an R/W control circuit 2 sets E<2>PROM 1 in a read modify mode, makes *CS (chip select signal) active and sets a read cycle. Addresses A0 to A7 to be written are inputted to the E<2>PROM 1. Thereby a read register 3 is made to hold data D0 to D7 at the time of the read cycle. A comparator circuit 4 compares these data with data WD0 to WD7 to be written. Only when they are not coincident, the R/W control circuit 2 makes a signal *WE in the next write cycle and writing is made in the E<2>PROM 1. In the case when they are coincident, *WE is not made active and the writing in the E<2>PROM is stopped. Accordingly, no rewriting of the same data is executed and thus the number of times of writing of data can be lessened to the necessary minimum.</p>
申请公布号 JPH0765586(A) 申请公布日期 1995.03.10
申请号 JP19930212419 申请日期 1993.08.27
申请人 IWAKI ELECTRON CORP LTD 发明人 KANEMOTO TETSUYA;WAKABAYASHI MASAMI;TAKAHASHI KAZUNORI;IIJIMA HIROSHIGE;TAKAHAGI HIROSHI;KUNII NOBUTAKA
分类号 G11C17/00;G11C16/02;G11C16/06;(IPC1-7):G11C16/06 主分类号 G11C17/00
代理机构 代理人
主权项
地址