| 摘要 |
PURPOSE:To reduce power consumption by simply composing a circuit for testing a multi-bit output at the time of a test mode. CONSTITUTION:An amplitude limiter 10i is connected between differential amplifiers Pi and PPi, the limiter 10i is operated at the time of read data in a normal mode to suppress an amplitude of a signal of a read data bus. At the time of a test mode, the limiter 10i is deactivated to increase an amplitude of the signal of the read data bus as compared with that at the time of the normal mode to simplify a testing circuit by a NAND circuit 56, number of differential amplifiers to be operated is reduced to suppress current consumption to increase as number of degeneracy is increased. |
