| 摘要 |
The current reduction circuit includes a pre-decoder consisting of an address input, an address buffer circuit receiving the address input signal, a NAND gate and an inverter, a X-decoder receiving the output of the pre-decoder and selecting a word line, a memory cell array consisting of a word line, a couple of bit lines, an N-channel transistor operating the bit lines and unit cell, an N-channel transistor employing the final stage of the word line as its gate terminal, a P-channel transistor whose drain is connected to the drain of the N-channel transistor, a delay connected between the drain of the N-channel transistor and the NAND gate of the pre-decoder, and an inverter connected between the drain of the N-channel transistor and sense amplifier.
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