发明名称 POWER CONSUMPTION REDUCING CIRCUIT
摘要 <p>PURPOSE:To provide a power consumption reducing circuit which can reduce the power consumption of a display without adding any special hardware. CONSTITUTION:A video signal monitor circuit 2 of a display 1 monitors the video signals received from a computer 8 and transmits a black image detecting signal to a timer circuit 4 if the video signals show an image of an entire black surface. Receiving the black image detecting signal from the circuit 2, the circuit 4 counts the clock pulses sent from an oscillator 3 and then transmits a power cut-off signal to a switch 6 when its count value is equal to the prescribed value. Then the switch 6 cuts the supply of power to a display device 7 in response to the power cut-off signal received from the circuit 4.</p>
申请公布号 JPH0756658(A) 申请公布日期 1995.03.03
申请号 JP19930220549 申请日期 1993.08.11
申请人 NEC CORP 发明人 SATO SHINOBU
分类号 G06F1/32;(IPC1-7):G06F1/32 主分类号 G06F1/32
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