发明名称 CLOCK GENERATING CIRCUIT
摘要 <p>PURPOSE:To shorten the waiting time when the output of an oscillation circuit is continuously supplied as a clock to a microprocessor at the start of oscillation until the output of the oscillation circuit is stabilized. CONSTITUTION:A clock generating circuit is provided with a 1st buffer circuit 2 which uses the output of an oscillation circuit 1 as its input and has the large hysteresis width, a 2nd buffer circuit 3 which uses the output of the circuit 1 as its input and has the small hystereis width, and a timer circuit 4 which uses the output of the circuit 2 as its count input. Then the output of the circuit 1 acquired through the circuit 3 is supplied to a microprocessor 7 via an AND circuit 6 when an overflow signal of the circuit 4 is produced.</p>
申请公布号 JPH0756649(A) 申请公布日期 1995.03.03
申请号 JP19930203452 申请日期 1993.08.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 MIO MASAO
分类号 G06F1/04;H03K21/08;H03L3/00;(IPC1-7):G06F1/04 主分类号 G06F1/04
代理机构 代理人
主权项
地址