| 摘要 |
PURPOSE:To delay an output of a data signal by writing a data signal in only one shift register decided uniquely by an output signal of a counter and holding a written data signal in a storage element when the next output signal of the counter becomes the same state. CONSTITUTION:A data shifting circuit is constituted with plural shift registers 1-4 in which the number of stages are equal, a storage element 8, a N-ary counter 5 which is operated by a clock signal from an external circuit, a clock signal distributor 6 which output a clock signal to only a register uniquely decided out of registers of 1-4 by the output signal, and a selector 7 which selects and outputs the signal. In the data shifting circuit, a data signal is written in only a register uniquely decided by an output signal of the counter 5, when the next output signal of the counter becomes the same state as the before, the data signal is held in the element 8. Thereby, output of a signal can be delayed by the time in which an output of the counter becomes the same state again. |
