| 摘要 |
<p>PURPOSE:To prevent duplex interruption by synchronizing interruption at a multiprocessor system by adding a hardware for widening the pulse duration of a real-time clock to be sent to a processor. CONSTITUTION:A counter 1 counts the number of clock pulses CP and when the number overflows, an interruption signal (INTL) is outputted from an RC pin. On the other hand, the real-time clock (RTC) of the interruption signal in a cycle T1 is inputted to a load pin LD, the count value of the counter 1 is preset to '0' and it is outputted to a bus as the interruption signal. Therefore, the counter 1 alternately repeats the overflow and the preset, and the interruption signal INTL in a prescribed cycle T2 is generated. since a ratio between the cycle T1 of the interruption signal RTC and the cycle T2 of the interruption signal INTL is set equally to an integral value, the interruption signals RTC and INTL are simultaneously outputted once the cycle of the interruption signal INTL.</p> |
