| 摘要 |
<p>PURPOSE:To decrease the circuit scale and to shorten the time up to the completion of frame synchronization by providing a frame synchronizing circuit which detects the positions of bits for frame synchronization by a multiple-bit simultaneous comparing process system by the channels of signals inputted through a parallel transmission line and performs a frame synchronizing process. CONSTITUTION:Once the positions of a frame bit is detected in a master channel, its frame position signal is sent to respective frame synchronizing circuits 10. The respective frame synchronizing circuits 10 finds the position of a frame bit inputted to itself on the basis of the frame position through parallel comparing process operation (simultaneous comparing process operation) handling several precedent and following bits. Consequently, the time up to the completion of frame synchronization is shortened. Further, the frame synchronizing circuits 10 need to be provided with frame counters only for the master channels, so the circuit scan can be decreased. Thus, data of respective selected channels are decoded by a decoding part 20 and outputted.</p> |
